EP910LC-35H vs EP910DC-40 Vergleich

Detaillierter Direktvergleich von EP910LC-35H von Altera und EP910DC-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910LC-35H EP910DC-40
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $25,00 $13,95
Family Classic EPLD (EP910) —
Logic Elements 24 macrocells —
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, UV-erasable EPROM —
Gehäuse 40-pin Ceramic DIP (H suffix) DIP-40 (ceramic, through-hole)
User I/O Pins 36 —
Dedicated Inputs 10 12
Betriebstemperatur [DATA_NEEDED: operating temperature range grade] —
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer UV-erase + EPROM programmer; on-board logic test circuitry
Logic Levels TTL compatible —
Ruhestrom [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Montageart Through-hole (Ceramic DIP) Through-Hole
RoHS-Status unknown [DATA_NEEDED: rohs_status]
Lifecycle Obsolete (long-term supply via Rochester Electronics) —
Device Family — Classic EPLD (EP910 series)
Architecture — PAL-type AND/OR, UV-erasable CMOS
Macrocells — 24
Bidirectional I/O Pins — 24
Total Inputs to Logic Array — 36
Product Terms — 240 maximum
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Versorgungsspannung — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C

Datenblätter & Ressourcen

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