EP910LC-35H vs EP910LC-40H Vergleich

Detaillierter Direktvergleich von EP910LC-35H von Altera und EP910LC-40H von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910LC-35H EP910LC-40H
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $25,00 $9,95
Family Classic EPLD (EP910) Classic EPLD (EP910)
Logic Elements 24 macrocells 24 macro cells / expandable to 48 via expander terms
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM
Gehäuse 40-pin Ceramic DIP (H suffix) 40-pin Ceramic DIP (CDIP-40), JEDEC standard
User I/O Pins 36 —
Dedicated Inputs 10 —
Betriebstemperatur [DATA_NEEDED: operating temperature range grade] -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade]
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer UV-erase + EPROM program, ~100 erase cycles
Logic Levels TTL compatible —
Ruhestrom [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Montageart Through-hole (Ceramic DIP) Through-Hole (THT)
RoHS-Status unknown [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP]
Lifecycle Obsolete (long-term supply via Rochester Electronics) —
Macro Cells — 24
Usable Gates — 450
Propagation Delay (tPD) — 40 ns max
Supply Current (ICC) — Low-power CMOS, typical ICC < 100 mA
Speed Grade — -40 (40 ns tPD)
I/O Pins — [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical]

Datenblätter & Ressourcen

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