EP910LC-35H vs EP910LC-40H Comparación
Comparación detallada lado a lado de EP910LC-35H por Altera y EP910LC-40H por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-35H | EP910LC-40H |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,00 | $9,95 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Elements | 24 macrocells | 24 macro cells / expandable to 48 via expander terms |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
| Encapsulado | 40-pin Ceramic DIP (H suffix) | 40-pin Ceramic DIP (CDIP-40), JEDEC standard |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range grade] | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] |
| Erasure Method | UV (quartz window on H package) | — |
| Programming Method | Altera hardware programmer | UV-erase + EPROM program, ~100 erase cycles |
| Logic Levels | TTL compatible | — |
| Corriente en reposo | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| Tipo de montaje | Through-hole (Ceramic DIP) | Through-Hole (THT) |
| Estado RoHS | unknown | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Macro Cells | — | 24 |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 40 ns max |
| Supply Current (ICC) | — | Low-power CMOS, typical ICC < 100 mA |
| Speed Grade | — | -40 (40 ns tPD) |
| I/O Pins | — | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] |