EP910LI-35T vs EP910LC-35T Vergleich
Detaillierter Direktvergleich von EP910LI-35T von Intel und EP910LC-35T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP910LI-35T - 24-Macrocell Classic EPLD 35ns 44-PLCC | Intel
EP910LI-35T ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP910LI-35T | EP910LC-35T |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $28,50 | $28,90 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Elements | 24 macrocells | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Toggle Frequency (fMAX) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, EPROM-based | — |
| Gehäuse | 44-pin PLCC (JEDEC) | PLCC-44 (J-lead) |
| Betriebstemperatur | -40C to +85C (industrial, 'I' suffix) | 0C to +70C (commercial) |
| Montageart | Surface Mount / Socket | Surface Mount (PLCC socket or solder) |
| Programming Method | EPROM (UV-erasable for windowed versions) | — |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| Number of I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status not in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Capacity | — | 450 usable gates |
| Macrocells | — | 24 |
| Maximum Operating Frequency | — | 28.6 MHz |
| User I/O Pins | — | 36 |
| Process Technology | — | CMOS (EPROM-based) |
| Erasure Method | — | UV-erasable window (ceramic package) / OTP (plastic) |
| Programming | — | Altera programming hardware + MAX+PLUS II |
| MSL-Level | — | MSL 3 (168 hours) |