EP910LI-40 vs EP910DC-40 Vergleich
Detaillierter Direktvergleich von EP910LI-40 von Altera und EP910DC-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910LI-40 | EP910DC-40 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,90 | $13,95 |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 bidirectional | — |
| Maximum Logic Inputs | 36 | — |
| Product Terms | 240 | 240 maximum |
| Propagation Delay (tPD) | 40 ns | — |
| Technology | Low-power CMOS (L-suffix) | — |
| Betriebstemperatur | -40C to +85C (industrial, I-suffix) | — |
| Gehäuse | PLCC-44 (J-lead, windowed ceramic) | DIP-40 (ceramic, through-hole) |
| Montageart | Surface Mount (socket-compatible) | Through-Hole |
| Programmability | UV-erasable, JEDEC-standard algorithm | — |
| RoHS-Status | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: rohs_status] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Versorgungsspannung | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |