EP910LI-40 vs EP910DC-40 Comparaison
Comparaison détaillée côte à côte de EP910LI-40 par Altera et EP910DC-40 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910LI-40 | EP910DC-40 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,90 | $13,95 |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 bidirectional | — |
| Maximum Logic Inputs | 36 | — |
| Product Terms | 240 | 240 maximum |
| Propagation Delay (tPD) | 40 ns | — |
| Technology | Low-power CMOS (L-suffix) | — |
| Température de fonctionnement | -40C to +85C (industrial, I-suffix) | — |
| Boîtier | PLCC-44 (J-lead, windowed ceramic) | DIP-40 (ceramic, through-hole) |
| Type de montage | Surface Mount (socket-compatible) | Through-Hole |
| Programmability | UV-erasable, JEDEC-standard algorithm | — |
| Statut RoHS | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: rohs_status] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Tension d'alimentation | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |