EP910PC-20 vs EP910PC-25 Vergleich
Detaillierter Direktvergleich von EP910PC-20 von Altera und EP910PC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-20 | EP910PC-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,40 | $16,92 |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Usable Gates | 900 | 900 |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | 25 ns |
| Gehäuse | PDIP-24 (PC suffix) | PDIP-24 (Plastic DIP) |
| Pin-Anzahl | 24 | 24 |
| Supply Voltage (VCC) | 5 V | 5 V +/- 10% |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM |
| I/O Compatibility | 100% TTL | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | EPROM programmer, JEDEC fuse map | — |
| Montageart | Through-Hole (DIP) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Product Family | — | Classic EPLD |
| Integration Gates (typical) | — | 4800 |
| Macrocells | — | 24 |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |