EP910PC-20 - Classic EPLD, 900 Gates, 20ns DIP-24 | Altera
Teilenummer: EP910PC-20 ✗ Abgekündigt| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $28.2 | $28,20 |
| 10 | $24.5 | $245,00 |
| 100 | $19.9 | $1.990,00 |
| 500 | $15.8 | $7.900,00 |
| 1.000 | $12.4 | $12.400,00 |
EP910PC-20 Übersicht
A Classic EPLD (Erasable Programmable Logic Device) is a one-time-programmable (windowed EPROM-based) or UV-erasable CMOS PLD that replaces discrete SSI/MSI logic and small PAL/GAL arrays. EPLDs sit in the programmable logic hierarchy below CPLDs and FPGAs, offering non-volatile, deterministic logic with predictable timing. The Classic family specifically targets pin-to-pin speeds competitive with TTL and 74-series logic while consuming CMOS standby power.
Key features of the EP910PC-20 include 24 pins, 16 dedicated inputs and 8 dedicated outputs (configurable as I/O depending on family mode), 900 usable gates, 100% TTL compatibility, and a 20 ns worst-case tPD (suffix "-20" speed grade). The part is fabricated on advanced CMOS technology and provides pin-to-pin logic delays suitable for state-machine decoding, address decoding, and bus-interface glue logic. The EP910 family integrates 300 to 900 usable gates, replacing multiple PAL/GAL devices with a single package.
The EP910 architecture combines a sum-of-products AND/OR array with output macrocells featuring programmable polarity, registered or combinatorial outputs, and feedback paths. Programming is performed via a standard EPROM programmer using the JEDEC fuse-map format, and the device is non-volatile at power-up. The Classic family includes 100% TTL I/O compatibility and supports both 5V-only and mixed-voltage system designs.
Typical applications include address decoding for microprocessor systems, bus arbitration, state-machine controllers, peripheral interface glue logic, and replacement of multiple PAL/GAL devices with a single EPLD. The PDIP-24 footprint supports through-hole PCB assembly, breadboard prototyping, and legacy system maintenance where socketed logic must remain in place.
Designers should select the -20 speed grade when a 20 ns maximum tPD is sufficient for the target system clock or address-to-enable timing. Slower grades (-25, -30, -35) offer lower cost where timing margins permit. Faster -15 and -12 grades exist for tighter timing budgets.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in-Alternativen für EP910PC-20 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit EP910PC-20 (gleiche Bauform und Footprint) – abweichend in Package, Programming Method, Supply Voltage (VCC), Mounting Type, Usable Gates.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
EP910PC-15
✅ Drop-In✓ Auf Lager
$12.8 / Stück
Datenblatt ansehen →EP910PC-12
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
EP910PC-0
✅ Drop-In✓ Auf Lager
$8.7 / Stück
Datenblatt ansehen →EP910IPC-25
✅ Drop-In✓ Auf Lager
$10.4 / Stück
Datenblatt ansehen →EP910IPC-15
✅ Drop-In✓ Auf Lager
$7.95 / Stück
Datenblatt ansehen →EP910PC-20 Grenzwerte & elektrische Eigenschaften
| Family | Altera Classic EPLD |
| Device | EP910 |
| Usable Gates | 900 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Gehäuse | PDIP-24 (PC suffix) |
| Pin-Anzahl | 24 |
| Supply Voltage (VCC) | 5 V |
| Technology | CMOS EPROM (UV-erasable) |
| I/O Compatibility | 100% TTL |
| Betriebstemperatur | 0C to +70C (commercial) |
| Programming Method | EPROM programmer, JEDEC fuse map |
| Montageart | Through-Hole (DIP) |
EP910PC-20 Pin-Konfiguration
| Pin 1 | I/O — Bidirectional I/O pin (programmable) |
| Pin 2 | I/O — Bidirectional I/O pin (programmable) |
| Pin 3 | I/O — Bidirectional I/O pin (programmable) |
| Pin 4 | I/O — Bidirectional I/O pin (programmable) |
| Pin 5 | I/O — Bidirectional I/O pin (programmable) |
| Pin 6 | I/O — Bidirectional I/O pin (programmable) |
| Pin 7 | I/O — Bidirectional I/O pin (programmable) |
| Pin 8 | I/O — Bidirectional I/O pin (programmable) |
| Pin 9 | I/O — Bidirectional I/O pin (programmable) |
| Pin 10 | GND — Ground (0 V) |
| Pin 11 | I/O — Bidirectional I/O pin (programmable) |
| Pin 12 | I/O — Bidirectional I/O pin (programmable) |
| Pin 13 | I/O — Bidirectional I/O pin (programmable) |
| Pin 14 | I/O — Bidirectional I/O pin (programmable) |
| Pin 15 | I/O — Bidirectional I/O pin (programmable) |
| Pin 16 | I/O — Bidirectional I/O pin (programmable) |
| Pin 17 | I/O — Bidirectional I/O pin (programmable) |
| Pin 18 | I/O — Bidirectional I/O pin (programmable) |
| Pin 19 | I/O — Bidirectional I/O pin (programmable) |
| Pin 20 | VCC — +5 V supply voltage |
| Pin 21 | I/O — Bidirectional I/O pin (programmable) |
| Pin 22 | I/O — Bidirectional I/O pin (programmable) |
| Pin 23 | I/O — Bidirectional I/O pin (programmable) |
| Pin 24 | I/O — Bidirectional I/O pin (programmable) |
Typische Anwendungen
EP910PC-20 ist geeignet für 6 Anwendungs: Microprocessor Address Decoding, Bus Arbitration Logic, State Machine Controllers, PAL/GAL Replacement, Peripheral Interface Glue Logic, Legacy System Maintenance.
Microprocessor Address Decoding
The EP910PC-20's 900 usable gates and 20 ns tPD make it suitable for microprocessor address decoding in legacy 8-bit and 16-bit systems such as 8086, 68k, and Z80 platforms. Its 24 pins provide ample I/O for decoding up to 24 address or control lines, replacing multiple 74LS138 decoder ICs. The TTL-compatible outputs drive bus buffers and chip-select lines directly without external pull-ups. JEDEC fuse-map programming simplifies integration with standard EPROM programmers.
Empfohlen
Bus Arbitration Logic
The EP910PC-20 integrates multi-master bus arbitration in 24-pin PDIP for systems such as ISA, VME, and Multibus. Its 100% TTL compatibility interfaces directly with bus transceivers and DMA controllers. With 20 ns tPD, the device propagates bus-request and bus-grant signals within budget for legacy bus clocks. The 900 gates replace discrete flip-flops and combinational glue logic in a single socketed package, simplifying board layout.
Empfohlen
State Machine Controllers
The EP910PC-20 implements complex state machines with up to 16 states in legacy control applications such as industrial controllers, test equipment, and peripherals. Its macrocell-based architecture with registered outputs and feedback simplifies FSM design. The 20 ns tPD supports state-transition rates up to 50 MHz in optimal conditions. Non-volatile EPROM-based configuration boots deterministically without external configuration memory.
Empfohlen
PAL/GAL Replacement
The EP910PC-20 consolidates 3 to 6 small PAL or GAL devices into a single 24-pin PDIP, reducing board area and improving reliability. Its 900 usable gates integrate AND/OR arrays with programmable polarity and registered outputs. JEDEC fuse-map compatibility supports existing design files without conversion. This application is common in cost-down redesigns of legacy systems where multiple PALCE16V8 or GAL20V8 devices occupied adjacent sockets.
Empfohlen
Peripheral Interface Glue Logic
The EP910PC-20 replaces discrete SSI/MSI glue logic in peripheral cards such as disk controllers, network adapters, and serial interfaces. Its 24 pins handle command decoding, interrupt steering, and control-signal conditioning. TTL-compatible outputs drive opto-isolators and line drivers directly. The 5V CMOS technology matches legacy peripheral rails; designers benefit from reduced component count versus discrete 74LS00/74LS04 implementations.
Empfohlen
Legacy System Maintenance
The EP910PC-20 supports field-replacement and maintenance of legacy systems where original parts are no longer manufactured. Its PDIP-24 through-hole package allows socketed substitution without PCB rework. The 20 ns speed grade matches original design timing across most legacy architectures including Multibus, VME, and STD bus systems. Long-term availability through distributors extends the operational life of industrial and aerospace systems built in the 1980s and 1990s.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für EP910PC-20 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | EP910PC-15 | EP910PC-12 | EP910PC-0 | EP910IPC-25 | EP910IPC-15 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PDIP-24 | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same |
| Usable Gates | 900 | 900 (same) | 900 (same) | 900 (same) | 900 (same) | 900 (same) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| I/O Compatibility | 100% TTL | 100% TTL (same) | 100% TTL (same) | 100% TTL (same) | 100% TTL (same) | 100% TTL (same) |
| Pin Count | 24 | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) |
Wichtigste Unterscheidungsmerkmale
- Faster timing-grade alternatives exist in same package (vs. EP910PC-15)
- Industrial temperature variants available in same package (vs. EP910IPC-25)
- Surface-mount equivalent for SMT boards (vs. EP910LC-35)
Designhinweise
The EP910PC-20 is obsolete and no longer factory-produced. Do not specify this part for new designs; instead, use MAX II EPM240T100C5N (TQFP-100) for active-lifecycle replacements, or same-family EP910PC-15 for direct drop-in maintenance of existing systems. Verify authenticity documentation when sourcing from secondary distributors, as obsolete parts attract counterfeit activity.
The EP910PC-20 operates from a single 5V supply. Decouple VCC (pin 20) with a 0.1uF ceramic capacitor placed within 5mm of the pin, plus a 10uF bulk capacitor near the supply entry point. The CMOS technology draws low standby current (typically tens of mA), but unused I/O pins should be configured as outputs to minimize supply current during operation.
For high-speed designs approaching the 20 ns tPD limit, place the EP910PC-20 socket close to the driven devices to minimize trace delay and ringing. The TTL-compatible outputs can drive 10 to 20 LSTTL loads, but long traces benefit from series damping resistors (22-33 ohm). Keep programming pins (if accessible) away from high-frequency signal paths to avoid noise coupling during in-circuit programming.
Compliance-Informationen
Compliance data not available in verified sources for this legacy part. EP910 family predates widespread RoHS adoption. Contact Intel FPGA (formerly Altera) for historical compliance documentation if required.
