EP910PI-15T vs EP910PC-15T Vergleich

Detaillierter Direktvergleich von EP910PI-15T von Altera und EP910PC-15T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910PI-15T EP910PC-15T
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,95 $14,20
Product Type Classic EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD (EP910 series) Altera Classic EPLD
Macrocells 24 —
Dedicated Inputs 12 —
I/O Pins 24 —
Logic Blocks 6 LABs of 4 macrocells each (Classic architecture) —
Versorgungsspannung 4.5 V to 5.5 V (5 V nominal) —
Propagation Delay (tPD) 15 ns max (speed grade -15) —
Technology CMOS EEPROM (electrically erasable) CMOS, UV-erasable / OTP
Gehäuse 40-pin PDIP (Plastic DIP, R-PDIP-T40) 40-pin PDIP (Plastic DIP)
Montageart Through-Hole Through-hole (DIP)
Output Drive Current [DATA_NEEDED: per-pin DC output current, mA] [DATA_NEEDED: IOL per output]
Betriebstemperatur [DATA_NEEDED: industrial/commercial temp range] 0C to +70C (commercial)
Programming JEDEC-standard, serial/parallel programmer —
RoHS-Status [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] [DATA_NEEDED: RoHS compliance status]
Macrocell Count — 24
Dedicated Input Pins — 10
Pin-to-Pin Delay (tPD) — 15 ns
Speed Grade — -15 (15 ns)
Supply Voltage (VCC) — 5 V (nominal)
Logic Capacity — 24 macrocells / 72 product terms (typical Classic architecture)
Programming Method — JEDEC fuse map via Altera LogicMap / MAX+PLUS II
Lead-Free — [DATA_NEEDED: lead-free status]
Security Bit — Yes (design protection)
Tape and Reel — Yes (suffix T)

Datenblätter & Ressourcen

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