EP910PI-15T vs EP910PC-15T Comparison

Detailed side-by-side comparison of EP910PI-15T by Altera and EP910PC-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910PI-15T EP910PC-15T
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.95 $14.20
Product Type Classic EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD (EP910 series) Altera Classic EPLD
Macrocells 24 β€”
Dedicated Inputs 12 β€”
I/O Pins 24 β€”
Logic Blocks 6 LABs of 4 macrocells each (Classic architecture) β€”
Supply Voltage 4.5 V to 5.5 V (5 V nominal) β€”
Propagation Delay (tPD) 15 ns max (speed grade -15) β€”
Technology CMOS EEPROM (electrically erasable) CMOS, UV-erasable / OTP
Package 40-pin PDIP (Plastic DIP, R-PDIP-T40) 40-pin PDIP (Plastic DIP)
Mounting Type Through-Hole Through-hole (DIP)
Output Drive Current [DATA_NEEDED: per-pin DC output current, mA] [DATA_NEEDED: IOL per output]
Operating Temperature [DATA_NEEDED: industrial/commercial temp range] 0C to +70C (commercial)
Programming JEDEC-standard, serial/parallel programmer β€”
RoHS Status [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] [DATA_NEEDED: RoHS compliance status]
Macrocell Count β€” 24
Dedicated Input Pins β€” 10
Pin-to-Pin Delay (tPD) β€” 15 ns
Speed Grade β€” -15 (15 ns)
Supply Voltage (VCC) β€” 5 V (nominal)
Logic Capacity β€” 24 macrocells / 72 product terms (typical Classic architecture)
Programming Method β€” JEDEC fuse map via Altera LogicMap / MAX+PLUS II
Lead-Free β€” [DATA_NEEDED: lead-free status]
Security Bit β€” Yes (design protection)
Tape and Reel β€” Yes (suffix T)

Datasheets & Resources

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