EPC1064LC20 vs EPC1213LI20 Vergleich

Detaillierter Direktvergleich von EPC1064LC20 von Intel und EPC1213LI20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC1064LC20 EPC1213LI20
Marke Intel Intel
Kategorie Memory ICs Memory ICs
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,85 $9,75
Speichergröße 65 kb (65,536 bits) 212 Kbit
Speichertyp OTP Configuration PROM (Flash-based, one-time programmable) OTP Configuration PROM (non-volatile)
Programmable Type OTP (One-Time Programmable) —
Schnittstelle Serial (Passive Serial / daisy-chain compatible) —
Access Time 90 ns (approximately 10 MHz) —
Supply Voltage (Operating) 4.5 V to 5.5 V —
Supply Voltage (Nominal) 5 V —
Betriebstemperatur 0 C to 70 C (Commercial) -40C to +85C (industrial)
Gehäuse / Bauform 20-PLCC (LC) J-lead, 9x9 mm —
No. of Terminals 20 —
Terminal Finish Tin/Lead (Sn/Pb) —
Package Code QCCJ (PLCC-20 J-lead) —
Package Shape Square —
Compatible Altera FPGA Families ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
Configuration Modes Supported Passive Serial (PS) with FPP up to 100 MHz on newer FPGAs —
RoHS-Status Non-compliant (Sn/Pb finish) [DATA_NEEDED: RoHS status - legacy Altera part]
MSL-Level [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL level]
Lead-Free No (Sn/Pb terminal finish) [DATA_NEEDED: lead-free status]
Schnittstellentyp — Serial (Altera active-serial configuration)
Supply Voltage (VCC) — 3.3 V / 5 V
I/O Voltage Tolerance — 3.3 V or 5 V
Programmability — OTP (one-time programmable)
Gehäuse — 20-PLCC (9x9 mm), J-lead
Pin-Anzahl — 20
Compatible FPGA Families — ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Configuration Mode — Active Serial (AS)
Internal Oscillator — Yes (generates DCLK to FPGA)
Cascade Support — Yes (nCASC pin for multi-device chains)

Datenblätter & Ressourcen

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