EPC1213LC20 vs EPC1LC20U Vergleich
Detaillierter Direktvergleich von EPC1213LC20 von Intel und EPC1LC20U von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC1213LC20 | EPC1LC20U |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | EEPROM | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,40 | $9,75 |
| Speichertyp | OTP Configuration PROM (Flash-based) | OTP (One-Time-Programmable) Configuration PROM |
| Speichergröße | 212 Kbit | — |
| Schnittstelle | Serial (Altera FPGA configuration protocol) | — |
| Maximum Configuration Clock | 6 MHz | — |
| Supply Voltage (Core) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V / 5.0 V | — |
| Programmability | One-Time Programmable (OTP) via IEEE 1149.1 JTAG | — |
| In-System Programmability | Yes (5.0 V and 3.3 V ISP) | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Compression Support | Yes (FPGA decompresses bitstream during load) | — |
| Betriebstemperatur | 0C to +70C (Commercial) | [DATA_NEEDED: industrial/commercial grade range] |
| Gehäuse | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (9x9 mm) |
| Package Code | QCCJ | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | Compliant (Pb-free finish, "U" suffix) |
| Memory Density | — | 1 Mbit |
| Configuration Interface | — | Altera Serial Configuration (4-wire) |
| Maximum DCLK Frequency | — | 8 MHz |
| Operating Voltage (VCC) | — | 3.3 V typical [DATA_NEEDED: full range] |
| Configuration Time | — | [DATA_NEEDED: depends on bitstream length and DCLK] |
| Cascading Support | — | Yes (multi-PROM daisy-chain for larger bitstreams) |
| Programming Method | — | Altera APU / third-party JTAG programmer |
| Lead-Free (Pb-free) Finish | — | Yes ("U" suffix) |
| Compatibility | — | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) |
| MSL-Level | — | [DATA_NEEDED] |