EPC1213LC20 vs EPC1LC20U 对比

详细并排对比 EPC1213LC20 出自 Intel 和 EPC1LC20U 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC1213LC20 EPC1LC20U
品牌 Intel Altera
分类 EEPROM Memory ICs
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $7.40 $9.75
存储器类型 OTP Configuration PROM (Flash-based) OTP (One-Time-Programmable) Configuration PROM
存储容量 212 Kbit —
接口 Serial (Altera FPGA configuration protocol) —
Maximum Configuration Clock 6 MHz —
Supply Voltage (Core) 5.0 V —
I/O Voltage Tolerance 3.3 V / 5.0 V —
Programmability One-Time Programmable (OTP) via IEEE 1149.1 JTAG —
In-System Programmability Yes (5.0 V and 3.3 V ISP) —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
Compression Support Yes (FPGA decompresses bitstream during load) —
工作温度 0C to +70C (Commercial) [DATA_NEEDED: industrial/commercial grade range]
封装 20-PLCC (J-lead, 9x9 mm) 20-pin PLCC (9x9 mm)
Package Code QCCJ —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance status] Compliant (Pb-free finish, "U" suffix)
Memory Density — 1 Mbit
Configuration Interface — Altera Serial Configuration (4-wire)
Maximum DCLK Frequency — 8 MHz
Operating Voltage (VCC) — 3.3 V typical [DATA_NEEDED: full range]
Configuration Time — [DATA_NEEDED: depends on bitstream length and DCLK]
Cascading Support — Yes (multi-PROM daisy-chain for larger bitstreams)
Programming Method — Altera APU / third-party JTAG programmer
Lead-Free (Pb-free) Finish — Yes ("U" suffix)
Compatibility — Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families)
MSL 等级 — [DATA_NEEDED]

数据手册与资源

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