EPC16QI100 vs EPC16QI100TBAC Vergleich
Detaillierter Direktvergleich von EPC16QI100 von Altera und EPC16QI100TBAC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA
EPC16QI100TBAC ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC16QI100 | EPC16QI100TBAC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,40 | $15,95 |
| Speichergröße | 16 Mb (1048576 words) | — |
| Programmable Type | In System Programmable (ISP) | — |
| Versorgungsspannung | 3.3 V (core and I/O) | 3.3 V |
| Betriebsversorgungsspannung | 3.0 V to 3.6 V | — |
| Configuration Clock Frequency | 33 MHz | — |
| Schnittstelle | Serial | — |
| Gehäuse | 100-PQFP (20 x 14 mm) | 100-pin PQFP (20 x 14 mm) |
| Pin-Anzahl | 100 | — |
| Betriebstemperatur | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial) |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | Yes (IEEE 1149.1 boundary-scan and programming) |
| IEEE 1532 ISP Compliance | Yes | — |
| Jam STAPL Support | Yes | — |
| Montageart | Surface Mount | Surface Mount (PQFP) |
| Temperature Grade | Industrial | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Speichertyp | — | Flash (Enhanced Configuration Device) |
| Configuration Modes | — | Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) |
| Maximum Configuration Clock | — | 40 MHz |
| Number of Configuration Pages | — | Up to 8 (selectable via PGM[2..0]) |
| In-System Programmable | — | Yes (via JTAG / IEEE 1149.1) |
| Supported FPGA Families | — | Altera Stratix, Cyclone, Arria series |
| Data Compression | — | Supported (15-30% density gain depending on target FPGA) |
| MSL-Level | — | 3 (168 hours) |
| Lead-Free / RoHS | — | Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] |
| Dynamic Reconfiguration | — | Yes (page mode via PGM[2..0] pins) |
| Configuration Controller | — | Integrated |
| Programming Interface | — | JTAG / 4-wire passive serial |