EPC16UC88 vs EPC16U188N Vergleich

Detaillierter Direktvergleich von EPC16UC88 von Altera und EPC16U188N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC16UC88 EPC16U188N
Marke Altera Altera
Kategorie Memory ICs FPGA & CPLD
Lebenszyklusstatus Unknown Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $0,00 $19,95
Device Type In-system programmable configuration PROM for FPGAs —
Configuration Memory Capacity 16 Mb —
Versorgungsspannung 3.3 V core and I/O —
Gehäuse 88-UBGA (11x8) 188-ball Ultra FineLine BGA (UBGA)
Package Family UBGA —
In-System Programmability IEEE Std. 1532 compatible —
Programming Language Support Jam Standard Test and Programming Language (STAPL) —
JTAG Boundary Scan Supported —
nINIT_CONF Function Allows private JTAG instruction to start FPGA configuration —
Configuration Architecture Configuration controller and flash memory —
FPGA Configuration Use Automatic configuration after power-up or system initialization —
Data Output Configuration data output controlled by OE and nCS —
Output Control OE and nCS control tri-state buffer and address counter —
Montageart Surface mount Surface Mount (BGA)
Package Dimensions 11 mm x 8 mm —
RoHS-Status [DATA_NEEDED: RoHS status] Compliant
REACH Status [DATA_NEEDED: REACH status] —
Betriebstemperatur [DATA_NEEDED: operating temperature] -40C to +85C
Output Current [DATA_NEEDED: output current] —
Configuration Frequency [DATA_NEEDED: configuration frequency] —
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 qualification] —
Speichertyp — In-System Programmable Configuration PROM
Memory Density — 16 Mbit
FPGA Family Support — Altera Cyclone, Stratix, APEX series
Configuration Modes — FPP, PS, AS, JTAG
Decompression — Built-in (multiplier 1x, 2x, 4x)
Schnittstelle — Parallel Flash Interface (PIA), JTAG (IEEE 1149.1)
I/O Voltage Support — 1.8V, 2.5V, 3.3V, 5.0V
Endurance — 100,000 erase/program cycles
Data Retention — 20 years
Programming Interface — IEEE 1149.1 JTAG
MSL-Level — 3 (168 hours)

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