EPC16UC88 vs EPC16U88 Vergleich

Detaillierter Direktvergleich von EPC16UC88 von Altera und EPC16U88 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC16UC88 EPC16U88
Marke Altera Altera
Kategorie Memory ICs FPGA & CPLD
Lebenszyklusstatus Unknown Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $0,00 $11,85
Device Type In-system programmable configuration PROM for FPGAs —
Configuration Memory Capacity 16 Mb —
Versorgungsspannung 3.3 V core and I/O —
Gehäuse 88-UBGA (11x8) 88-ball UBGA (UltraBGA), 11x8 mm
Package Family UBGA —
In-System Programmability IEEE Std. 1532 compatible —
Programming Language Support Jam Standard Test and Programming Language (STAPL) —
JTAG Boundary Scan Supported —
nINIT_CONF Function Allows private JTAG instruction to start FPGA configuration —
Configuration Architecture Configuration controller and flash memory —
FPGA Configuration Use Automatic configuration after power-up or system initialization —
Data Output Configuration data output controlled by OE and nCS —
Output Control OE and nCS control tri-state buffer and address counter —
Montageart Surface mount —
Package Dimensions 11 mm x 8 mm —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
REACH Status [DATA_NEEDED: REACH status] —
Betriebstemperatur [DATA_NEEDED: operating temperature] -40C to +85C (industrial)
Output Current [DATA_NEEDED: output current] —
Configuration Frequency [DATA_NEEDED: configuration frequency] —
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 qualification] —
Memory Density — 16 Mb
Device Family — EPC16 (Enhanced Configuration Device)
Funktion — Configuration PROM for SRAM-based LUT FPGAs
Package Suffix Code — U88 (UBGA-88)
Supply Voltage (VCC) — 3.3 V
I/O Voltage Tolerance — 5 V tolerant I/O
Configuration Modes Supported — FPP, PS, AS (with target FPGA)
In-System Programming — Yes (IEEE 1149.1 JTAG)
Multi-Device Cascading — Yes (page-mode support)
Compatible FPGA Families — Altera Stratix, Cyclone, Arria series
Configuration Interface Width — Up to 8-bit parallel (FPP)
MSL-Level — [DATA_NEEDED: MSL moisture sensitivity level]

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern