EPC16UIC88 vs EPC16UC88 Vergleich
Detaillierter Direktvergleich von EPC16UIC88 von Altera und EPC16UC88 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC16UIC88 - 16Mb Enhanced Configuration Device | Altera/Intel
EPC16UIC88 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC16UIC88 | EPC16UC88 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Unknown |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,20 | $0,00 |
| Speichergröße | 16 Mb (1M x 16) | — |
| Speichertyp | Enhanced Configuration Device (flash-based, non-volatile) | — |
| Configuration Interface | Parallel CMOS, FPP mode for legacy Altera FPGAs | — |
| Supply Voltage (VCC) | 3.3 V | — |
| In-System Programmability | Yes, JTAG IEEE Std 1149.1 | IEEE Std. 1532 compatible |
| Program/Erase Cycles | [DATA_NEEDED: endurance spec] | — |
| Data Retention | 20 years minimum | — |
| Gehäuse | UBGA-88 (Ultra FineLine BGA), 11 x 8 mm | 88-UBGA (11x8) |
| Montageart | Surface Mount | Surface mount |
| Betriebstemperatur | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature] |
| Multi-Device Cascading | Yes, supports 2-device daisy-chain for 32 Mb | — |
| Configuration Handshake Pins | nCONFIG, nSTATUS, CONF_DONE | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: explicit RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free Reflow | Yes, peak reflow 260C per JEDEC J-STD-020 | — |
| Process Technology | CMOS, 3.3 V core | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Versorgungsspannung | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |