EPC16UIC88 vs EPC16UC88 Comparaison
Comparaison détaillée côte à côte de EPC16UIC88 par Altera et EPC16UC88 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16UIC88 | EPC16UC88 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Dernier achat | Unknown |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,20 | $0,00 |
| Taille de mémoire | 16 Mb (1M x 16) | — |
| Type de mémoire | Enhanced Configuration Device (flash-based, non-volatile) | — |
| Configuration Interface | Parallel CMOS, FPP mode for legacy Altera FPGAs | — |
| Supply Voltage (VCC) | 3.3 V | — |
| In-System Programmability | Yes, JTAG IEEE Std 1149.1 | IEEE Std. 1532 compatible |
| Program/Erase Cycles | [DATA_NEEDED: endurance spec] | — |
| Data Retention | 20 years minimum | — |
| Boîtier | UBGA-88 (Ultra FineLine BGA), 11 x 8 mm | 88-UBGA (11x8) |
| Type de montage | Surface Mount | Surface mount |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature] |
| Multi-Device Cascading | Yes, supports 2-device daisy-chain for 32 Mb | — |
| Configuration Handshake Pins | nCONFIG, nSTATUS, CONF_DONE | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Statut RoHS | [DATA_NEEDED: explicit RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free Reflow | Yes, peak reflow 260C per JEDEC J-STD-020 | — |
| Process Technology | CMOS, 3.3 V core | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tension d'alimentation | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |