EPC1LC20U vs EPC144LC20 Vergleich
Detaillierter Direktvergleich von EPC1LC20U von Altera und EPC144LC20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC1LC20U | EPC144LC20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $7,10 |
| Speichertyp | OTP (One-Time-Programmable) Configuration PROM | — |
| Memory Density | 1 Mbit | — |
| Configuration Interface | Altera Serial Configuration (4-wire) | — |
| Maximum DCLK Frequency | 8 MHz | — |
| Gehäuse | 20-pin PLCC (9x9 mm) | 20-pin LCC (Leadless Chip Carrier, JLCC-20) |
| Operating Voltage (VCC) | 3.3 V typical [DATA_NEEDED: full range] | — |
| Configuration Time | [DATA_NEEDED: depends on bitstream length and DCLK] | — |
| Cascading Support | Yes (multi-PROM daisy-chain for larger bitstreams) | — |
| Programming Method | Altera APU / third-party JTAG programmer | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) |
| Lead-Free (Pb-free) Finish | Yes ("U" suffix) | — |
| Montageart | Surface Mount | Surface Mount |
| Compatibility | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) | — |
| Betriebstemperatur | [DATA_NEEDED: industrial/commercial grade range] | -40C to +85C (industrial) |
| MSL-Level | [DATA_NEEDED] | 3 (168 hours) |
| RoHS-Status | Compliant (Pb-free finish, "U" suffix) | [DATA_NEEDED: RoHS compliance status per Intel PCN] |
| Memory Capacity | — | 144 Kbit |
| Memory Organization | — | Serial (one-time programmable) |
| Schnittstellentyp | — | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Supply Voltage (VCC) | — | 3.0 V to 5.5 V |
| Configuration Time (typical) | — | [DATA_NEEDED: configuration time at DCLK = 10 MHz] |
| Active Supply Current | — | [DATA_NEEDED: ICC active] |
| Standby Supply Current | — | [DATA_NEEDED: ICC standby] |
| Pin-Anzahl | — | 20 |
| Supported FPGA Families | — | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K |
| Lead-Free | — | Yes |
| Halogenfrei | — | [DATA_NEEDED] |
| JTAG Compliance | — | IEEE Std 1149.1 |