EPC1LC20U vs EPC144LC20 Comparaison
Comparaison détaillée côte à côte de EPC1LC20U par Altera et EPC144LC20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LC20U | EPC144LC20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $7,10 |
| Type de mémoire | OTP (One-Time-Programmable) Configuration PROM | — |
| Memory Density | 1 Mbit | — |
| Configuration Interface | Altera Serial Configuration (4-wire) | — |
| Maximum DCLK Frequency | 8 MHz | — |
| Boîtier | 20-pin PLCC (9x9 mm) | 20-pin LCC (Leadless Chip Carrier, JLCC-20) |
| Operating Voltage (VCC) | 3.3 V typical [DATA_NEEDED: full range] | — |
| Configuration Time | [DATA_NEEDED: depends on bitstream length and DCLK] | — |
| Cascading Support | Yes (multi-PROM daisy-chain for larger bitstreams) | — |
| Programming Method | Altera APU / third-party JTAG programmer | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) |
| Lead-Free (Pb-free) Finish | Yes ("U" suffix) | — |
| Type de montage | Surface Mount | Surface Mount |
| Compatibility | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) | — |
| Température de fonctionnement | [DATA_NEEDED: industrial/commercial grade range] | -40C to +85C (industrial) |
| Niveau MSL | [DATA_NEEDED] | 3 (168 hours) |
| Statut RoHS | Compliant (Pb-free finish, "U" suffix) | [DATA_NEEDED: RoHS compliance status per Intel PCN] |
| Memory Capacity | — | 144 Kbit |
| Memory Organization | — | Serial (one-time programmable) |
| Type d'interface | — | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Supply Voltage (VCC) | — | 3.0 V to 5.5 V |
| Configuration Time (typical) | — | [DATA_NEEDED: configuration time at DCLK = 10 MHz] |
| Active Supply Current | — | [DATA_NEEDED: ICC active] |
| Standby Supply Current | — | [DATA_NEEDED: ICC standby] |
| Nombre de broches | — | 20 |
| Supported FPGA Families | — | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K |
| Lead-Free | — | Yes |
| Sans halogène | — | [DATA_NEEDED] |
| JTAG Compliance | — | IEEE Std 1149.1 |