EPC21C20U vs EPC1LI20N Vergleich
Detaillierter Direktvergleich von EPC21C20U von Intel und EPC1LI20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC21C20U | EPC1LI20N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $7,80 |
| Manufacturer | Intel / Altera | — |
| Product Type | Configuration Device (Boot Flash) | — |
| Speichergröße | 20 Mbit (2.5 Mbyte) | 1 Mbit (1,048,576 bits) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| Schnittstelle | Altera/Intel Passive Serial (PS) and Active Serial (AS), JTAG (IEEE 1149.1) | — |
| Gehäuse | 20-pin UBGA (Ultra FineLine BGA) - also called 20-pin FBGA | — |
| In-System Programmability | Yes (via JTAG) | — |
| Bitstream Compression Support | Yes | — |
| Cascade (Multi-Device) Support | Yes (nCASC daisy-chain) | — |
| Supported FPGA Families | APEX II, APEX 20KE, APEX 20KC, Mercury, Stratix, Cyclone, ACEX 1K, FLEX 10KE | — |
| Betriebstemperatur | -40 C to +85 C (industrial) | -40C to +85C (Industrial) |
| Montageart | Surface Mount (BGA) | Surface Mount (PLCC socket or solder) |
| RoHS-Status | Compliant (per Intel/Altera product page) | Compliant |
| Lead-Free | Yes | — |
| Configuration Mode | Passive Serial (PS) / Active Serial (AS) via FPGA controller | — |
| Speichertyp | — | OTP Configuration PROM (One-Time Programmable) |
| Schnittstellentyp | — | Serial (Altera proprietary configuration protocol) |
| Gehäuse / Bauform | — | 20-LCC (J-Lead), PLCC-20 |
| Package Dimensions | — | 9 mm x 9 mm (PLCC-20 J-lead) |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage - VCCIO | — | 4.5 V to 5.5 V |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant (for programming) |
| Programmable Compression | — | Yes (reduces bitstream 30-55%) |
| Packaging | — | Tube |
| Lead Finish | — | Matte Sn (per JEDEC J-STD-020) |
| Target FPGA Families | — | Cyclone, FLEX 10K, APEX, ACEX 1K (LUT-based) |