EPC2L120 vs EPC2LC20 Vergleich
Detaillierter Direktvergleich von EPC2L120 von Altera und EPC2LC20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2L120 | EPC2LC20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,20 | $7,20 |
| Speichertyp | Configuration PROM (Flash-based) | Non-volatile configuration PROM |
| Density | 120 Kbit | — |
| Configuration Interface | Serial, FPGA-targeted | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Operating Voltage | 2.7 V to 3.6 V (3.3 V typ) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Gehäuse | PLCC-20 | 20-pin PLCC (J-lead, 9x9 mm) |
| Compatible FPGAs | Altera Cyclone, Cyclone II, APEX-series | — |
| Betriebstemperatur | -40 C to +85 C | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| CONF_DONE Output | Open-drain, wire-OR capable | — |
| Data Retention | 20 years (per Altera datasheet family) | — |
| Program/Erase Cycles | 100 cycles minimum | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | unknown | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free | unknown | — |
| Family | EPC2 (Enhanced Configuration) | — |
| Speichergröße | — | 1.6 Mbit |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |