EPC2L120 vs EPC2LC20 Perbandingan

Perbandingan bersamaan detil EPC2L120 dari Altera dan EPC2LC20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC2L120 EPC2LC20
Merek Altera Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup NRND NRND
Tipe Memori Configuration PROM (Flash-based) Non-volatile configuration PROM
Density 120 Kbit —
Configuration Interface Serial, FPGA-targeted Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Operating Voltage 2.7 V to 3.6 V (3.3 V typ) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Paket PLCC-20 20-pin PLCC (J-lead, 9x9 mm)
Compatible FPGAs Altera Cyclone, Cyclone II, APEX-series —
Suhu Kerja -40 C to +85 C -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
CONF_DONE Output Open-drain, wire-OR capable —
Data Retention 20 years (per Altera datasheet family) —
Program/Erase Cycles 100 cycles minimum —
Tipe Mounting Surface Mount Surface Mount
Status RoHS unknown Non-Compliant (original Altera Pb-containing part)
Lead-Free unknown —
Family EPC2 (Enhanced Configuration) —
Ukuran Memori — 1.6 Mbit
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC — 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range — 5.0 V or 3.3 V
Supported FPGA Families — ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Cascade Support — Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

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