EPC2L20N vs EPC2L20U-HAF480119C Vergleich
Detaillierter Direktvergleich von EPC2L20N von Altera und EPC2L20U-HAF480119C von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC2L20N | EPC2L20U-HAF480119C |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,20 | $10,75 |
| Funktion | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs | — |
| Speichergröße | 1.6 Mbit | 1.6 Mb |
| Programmable Type | In System Programmable (ISP) | — |
| Supply Voltage - VCCINT/VCCIO | 3.0 V to 3.6 V or 4.5 V to 5.5 V | — |
| Gehäuse / Bauform | 20-LCC (J-Lead), PLCC-20 | — |
| Packaging | Tube | — |
| Betriebstemperatur | 0C to +70C (commercial) | — |
| Supported FPGA Families | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) | — |
| Configuration Interface | Serial (Altera FPP / PS configuration scheme) | — |
| Cascade Support | Yes (multi-PROM chain via CE control) | Yes (multi-PROM chains for larger FPGAs) |
| Programming Method | In-system via 4-wire ISP / JTAG-style | — |
| Montageart | Surface Mount (J-Lead PLCC) | Surface Mount / Socketed |
| Pin-Anzahl | 20 | — |
| Lead Finish | Matte Tin (Pb-free) | — |
| MSL-Level | 3 (168 hours) | — |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS status] |
| Speichertyp | — | Configuration PROM (non-volatile) |
| Target Device | — | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) |
| Core Supply Voltage | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant |
| Configuration Modes | — | Serial (1-bit), Parallel (8-bit FPP), JTAG |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Programmability | — | In-system programmable via JTAG |
| Configuration Clock Range | — | 10 MHz to 40 MHz |
| Bitstream Compression Support | — | Yes (Cyclone/Stratix compressed bitstreams) |
| Gehäuse | — | PLCC-20 |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |