EPC2L20U vs EPC2L120N Vergleich
Detaillierter Direktvergleich von EPC2L20U von Altera und EPC2L120N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2L20U | EPC2L120N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,55 | $7,85 |
| Speichergröße | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Schnittstellentyp | Serial configuration (DCLK/DATA0) | — |
| Programmability | In-system programmable via IEEE 1532 / JTAG | — |
| Supported FPGAs | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K | — |
| Configuration Mode | Single + Cascade (multi-PROM daisy chain) | — |
| Compression Support | Yes (FPGA decompresses bitstream) | — |
| Betriebstemperatur | -40C to +85C (industrial) | [DATA_NEEDED: industrial temp range] |
| Gehäuse | 20-PLCC (PLCC-20) | 84-pin PLCC (J-Lead) |
| Montageart | Surface Mount / Socket | — |
| JTAG Support | Yes (IEEE Std 1149.1 boundary scan) | — |
| Pin-Anzahl | 20 | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | — | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |