EPC2L20U vs EPC2L120N Comparaison
Comparaison détaillée côte à côte de EPC2L20U par Altera et EPC2L120N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2L20U | EPC2L120N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,55 | $7,85 |
| Taille de mémoire | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Type d'interface | Serial configuration (DCLK/DATA0) | — |
| Programmability | In-system programmable via IEEE 1532 / JTAG | — |
| Supported FPGAs | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K | — |
| Configuration Mode | Single + Cascade (multi-PROM daisy chain) | — |
| Compression Support | Yes (FPGA decompresses bitstream) | — |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: industrial temp range] |
| Boîtier | 20-PLCC (PLCC-20) | 84-pin PLCC (J-Lead) |
| Type de montage | Surface Mount / Socket | — |
| JTAG Support | Yes (IEEE Std 1149.1 boundary scan) | — |
| Nombre de broches | 20 | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | — | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |