EPC2LC20 vs EPC1LC20HEC Vergleich
Detaillierter Direktvergleich von EPC2LC20 von Altera und EPC1LC20HEC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LC20 | EPC1LC20HEC |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,20 | $9,60 |
| Speichertyp | Non-volatile configuration PROM | OTP Configuration PROM (EEPROM-based) |
| Speichergröße | 1.6 Mbit | — |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | — |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | — |
| ISP Voltage Range | 5.0 V or 3.3 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | — |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | — |
| Gehäuse | 20-pin PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Montageart | Surface Mount | Surface Mount (PLCC socket recommended) |
| Betriebstemperatur | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | 0C to +70C (commercial) |
| RoHS-Status | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: RoHS status] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | — |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | — |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | — |
| Memory Density | — | 1 Mbit (1,048,576 bits) |
| Schnittstelle | — | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF) |
| Max Configuration Clock | — | 8 MHz |
| Versorgungsspannung | — | 3.3 V or 5 V |
| Programmability | — | One-Time Programmable (OTP) |
| Daisy Chain Support | — | Yes |
| nINIT_CONF Pin | — | Yes (programmable as nCONFIG or nSTATUS) |
| DONE Pin | — | Yes |
| Compatible FPGA Families | — | APEX, ACEX, FLEX, Cyclone (legacy) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |