EPC2LC20 vs EPC1LC20HEC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20 sa pamamagitan ng Altera at EPC1LC20HEC sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2LC20 | EPC1LC20HEC |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Uri ng Memory | Non-volatile configuration PROM | OTP Configuration PROM (EEPROM-based) |
| Laki ng Memory | 1.6 Mbit | — |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | — |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | — |
| ISP Voltage Range | 5.0 V or 3.3 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | — |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | — |
| Packhaging | 20-pin PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket recommended) |
| Temperature na Operasyon | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | 0C to +70C (commercial) |
| Tindminan RoHS | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: RoHS status] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | — |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | — |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | — |
| Memory Density | — | 1 Mbit (1,048,576 bits) |
| Interface | — | Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF) |
| Max Configuration Clock | — | 8 MHz |
| Volte ng Pagbibigay | — | 3.3 V or 5 V |
| Programmability | — | One-Time Programmable (OTP) |
| Daisy Chain Support | — | Yes |
| nINIT_CONF Pin | — | Yes (programmable as nCONFIG or nSTATUS) |
| DONE Pin | — | Yes |
| Compatible FPGA Families | — | APEX, ACEX, FLEX, Cyclone (legacy) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |