EPC2LC20CAD vs EPC2LC120 Vergleich
Detaillierter Direktvergleich von EPC2LC20CAD von Altera und EPC2LC120 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LC20CAD | EPC2LC120 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $9,95 |
| Speichertyp | Configuration PROM (Flash) | — |
| Memory Capacity | 1.6 Mbit | — |
| Versorgungsspannung | 3.3 V (nominal) | 3.3 V |
| I/O Voltage Tolerance | 5 V tolerant | — |
| Configuration Mode | Serial (bit-wide, Altera FPGAs) | — |
| Program Interface | IEEE Std 1149.1 JTAG (in-system programmable) | — |
| Gehäuse | 20-pin J-lead PLCC (PLCC-20) | PLCC-120 |
| Pin-Anzahl | 20 | 120 |
| Betriebstemperatur | -40C to +85C (commercial) | [DATA_NEEDED: operating temperature range] |
| Maximum Input Voltage (DC) | -0.3 V to +7.0 V | — |
| Input Undershoot/Overshoot | -2.0 V to +7.0 V for <100 mA, <20 ns no-load | — |
| Compatible FPGA Families | APEX 20K, ACEX 1K, Cyclone, Stratix | FLEX, ACEX, APEX, Mercury (Altera) |
| Programming Method | JTAG ISP (no external programmer required) | — |
| RoHS-Status | Compliant | — |
| Montageart | Surface Mount / Through-hole (PLCC socket) | Surface Mount / Socket |
| Funktion | — | FPGA Configuration Memory Device |
| Memory Density | — | 2 Mbit |
| Programming Interface | — | JTAG IEEE 1149.1 |
| Configuration Modes | — | PS (serial), PPA (parallel), multi-device daisy chain |
| Storage Temperature | — | [DATA_NEEDED: storage temperature] |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS status] |
| Data Compression Support | — | Yes (Altera proprietary, up to 2:1) |
| Remote Update Support | — | Yes (via JTAG multi-mode protocol) |