EPC2LI20J vs EPC2LI20U Vergleich
Detaillierter Direktvergleich von EPC2LI20J von Altera und EPC2LI20U von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LI20J | EPC2LI20U |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $7,10 |
| Speichertyp | In-System Programmable Configuration PROM (flash) | Configuration PROM (serial EEPROM) |
| Speichergröße | 1,695,680 bits (1.6Mb) | 1.6 Mbit (65,536 x 1-bit device) |
| Speicherorganisation | 65,536 x 1-bit (serial interface) | — |
| Schnittstelle | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) | — |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant | — |
| ISP Programming Interface | JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (multi-device configuration chain) | Yes (via nCASC pin) |
| Internal Oscillator | Yes (configures without external clock source) | — |
| Gehäuse | 20-pin PLCC with J-leads (JEDEC MS-018) | 20-pin PLCC (9x9 mm) |
| Betriebstemperatur | -40C to +85C (industrial) | — |
| Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Clock (DCLK) | Up to 33 MHz | — |
| Supply Voltage (VCC) | — | 3.0 V to 5.5 V (5.0 V nominal) |
| Programming Voltage | — | 5.0 V (via internal charge pump) |
| Configuration Interface | — | Serial 4-pin (DATA, DCLK, nCS, OE) |
| Maximum DCLK Frequency | — | 33 MHz (fast mode) |
| Betriebstemperaturbereich | — | -40 C to +85 C (industrial) |
| Montageart | — | Surface Mount (PLCC socket) |
| Programmability | — | In-system programmable via JTAG (IEEE 1149.1) |
| Device ID | — | 32-bit JTAG-readable |
| Supported FPGA Families | — | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| MSL-Level | — | [DATA_NEEDED: MSL moisture sensitivity level] |