EPC2LI20PULLS vs EPC2LI20J Vergleich
Detaillierter Direktvergleich von EPC2LI20PULLS von Intel und EPC2LI20J von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LI20PULLS | EPC2LI20J |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $9,75 |
| Speichertyp | Serial Configuration Flash PROM | In-System Programmable Configuration PROM (flash) |
| Speichergröße | 1.6 Mbit | 1,695,680 bits (1.6Mb) |
| Configuration Interface | Serial (Altera FPP / PS modes) | — |
| Maximale Taktfrequenz | 10 MHz | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Tolerance | 5 V tolerant configuration pins | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Compression Support | Yes (real-time decompression in target FPGA) | — |
| Multi-Device Cascade | Yes (daisy-chain supported) | — |
| Betriebstemperatur | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Gehäuse | 20-pin PLCC (J-Lead, 9x9 mm) | 20-pin PLCC with J-leads (JEDEC MS-018) |
| Montageart | Surface Mount / Socket | — |
| MSL-Level | 3 (168 hours) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur | — |
| Speicherorganisation | — | 65,536 x 1-bit (serial interface) |
| Schnittstelle | — | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) |
| Target FPGAs | — | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage (VCCIO) | — | 5.0 V or 3.3 V tolerant |
| ISP Programming Interface | — | JTAG (IEEE 1149.1) |
| Cascade Support | — | Yes (multi-device configuration chain) |
| Internal Oscillator | — | Yes (configures without external clock source) |
| Programming Cycles | — | [DATA_NEEDED: minimum endurance cycles] |
| Configuration Clock (DCLK) | — | Up to 33 MHz |