EPC2LI20PULLS vs EPC2LI20J Comparación
Comparación detallada lado a lado de EPC2LI20PULLS por Intel y EPC2LI20J por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LI20PULLS | EPC2LI20J |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $9,75 |
| Tipo de memoria | Serial Configuration Flash PROM | In-System Programmable Configuration PROM (flash) |
| Tamaño de memoria | 1.6 Mbit | 1,695,680 bits (1.6Mb) |
| Configuration Interface | Serial (Altera FPP / PS modes) | — |
| Frecuencia de reloj máxima | 10 MHz | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Tolerance | 5 V tolerant configuration pins | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Compression Support | Yes (real-time decompression in target FPGA) | — |
| Multi-Device Cascade | Yes (daisy-chain supported) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Encapsulado | 20-pin PLCC (J-Lead, 9x9 mm) | 20-pin PLCC with J-leads (JEDEC MS-018) |
| Tipo de montaje | Surface Mount / Socket | — |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur | — |
| Organización de memoria | — | 65,536 x 1-bit (serial interface) |
| Interfaz | — | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) |
| Target FPGAs | — | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage (VCCIO) | — | 5.0 V or 3.3 V tolerant |
| ISP Programming Interface | — | JTAG (IEEE 1149.1) |
| Cascade Support | — | Yes (multi-device configuration chain) |
| Internal Oscillator | — | Yes (configures without external clock source) |
| Programming Cycles | — | [DATA_NEEDED: minimum endurance cycles] |
| Configuration Clock (DCLK) | — | Up to 33 MHz |