EPC2LS20U vs EPC2L20 Vergleich
Detaillierter Direktvergleich von EPC2LS20U von Altera und EPC2L20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2LS20U | EPC2L20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,25 | $25,80 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| Schnittstelle | Altera serial configuration / JTAG | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| Gehäuse | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead) |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| Betriebstemperatur | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| MSL-Level | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL rating] |
| Compliance | RoHS (Pb-free per U suffix) | — |
| Speichertyp | — | Configuration PROM (non-volatile) |
| Speichergröße | — | 1.6 Mbit |
| Speicherorganisation | — | 8-bit byte |
| Programmability | — | In-system programmable via JTAG |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V (VCCSEL selectable) |
| Cascade Support | — | Yes - multi-device daisy chain |
| Boundary Scan | — | JTAG IEEE 1149.1 BST |
| Montageart | — | Surface Mount (PLCC socket compatible) |
| RoHS-Status | — | RoHS Compliant (per IC Components listing) |
| Process Technology | — | Low-power CMOS |
| Target FPGAs | — | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix |