EPC2LS20U vs EPC2L20 对比
详细并排对比 EPC2LS20U 出自 Altera 和 EPC2L20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC2LS20U | EPC2L20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | Memory ICs | Memory ICs |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.25 | $25.80 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| 接口 | Altera serial configuration / JTAG | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| 封装 | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead) |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| 工作温度 | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| MSL 等级 | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL rating] |
| Compliance | RoHS (Pb-free per U suffix) | — |
| 存储器类型 | — | Configuration PROM (non-volatile) |
| 存储容量 | — | 1.6 Mbit |
| 存储组织 | — | 8-bit byte |
| Programmability | — | In-system programmable via JTAG |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V (VCCSEL selectable) |
| Cascade Support | — | Yes - multi-device daisy chain |
| Boundary Scan | — | JTAG IEEE 1149.1 BST |
| 安装类型 | — | Surface Mount (PLCC socket compatible) |
| RoHS 状态 | — | RoHS Compliant (per IC Components listing) |
| Process Technology | — | Low-power CMOS |
| Target FPGAs | — | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix |