EPC2TC32CAF48 vs EPC2TC32HAF48 Vergleich
Detaillierter Direktvergleich von EPC2TC32CAF48 von Altera und EPC2TC32HAF48 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPC2TC32CAF48 - Altera/Intel Configuration Device for SRAM FPGAs | TQFP-48
EPC2TC32CAF48 ObsoleteSpezifikationsvergleich
| Parameter | EPC2TC32CAF48 | EPC2TC32HAF48 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $15,20 |
| Speichertyp | Non-volatile Flash (configuration) | — |
| Speichergröße | 32 Mbit | 32 Mbit (4 Mbyte) |
| Configuration Interface | Altera serial (PS mode) | Altera EPC serial (DATA, DCLK, nCONFIG, nSTATUS, nCASC) |
| Supply Voltage (VCC) | 3.3 V | 3.3 V (typical) |
| JTAG Support | Yes (IEEE 1149.1 ISP) | — |
| Cascadable | Yes (up to 16 devices) | — |
| Target FPGA Series | APEX II, Mercury, Cyclone, Stratix, ACEX, APEX 20K | — |
| Gehäuse | TQFP-48 (CAF48) | TQFP-48 (7x7x1.0 mm) |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant | — |
| Lead Free | Yes | — |
| MSL-Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Programming Voltage | 3.3 V (in-system via JTAG) | — |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | EPC2 (Enhanced Configuration Device, 2nd generation) | — |
| Funktion | — | FPGA Configuration PROM for SRAM-based LUT devices |
| In-System Programmability | — | Yes, via JTAG (IEEE 1149.1) |
| Cascade Support | — | Yes, multi-device daisy-chain via nCASC |
| FPGA Compatibility | — | Altera/Intel Cyclone, Stratix, APEX, ACEX families |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free / RoHS status] |
| Programming Cycles | — | [DATA_NEEDED: program/erase endurance] |
| Configuration Clock (DCLK) | — | [DATA_NEEDED: maximum DCLK frequency] |
| Configuration Time (typical) | — | [DATA_NEEDED: configuration time] |