EPC80C100 vs EPC80C100T Vergleich
Detaillierter Direktvergleich von EPC80C100 von Intel und EPC80C100T von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC80C100 | EPC80C100T |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $24,10 | $25,40 |
| Device Type | Enhanced Configuration (EPC) Memory | — |
| Configuration Memory Size | 80 Mbit | — |
| Target FPGA Families | Cyclone, Cyclone II, Stratix, APEX 20K, ACEX 1K | — |
| Configuration Modes Supported | Passive Serial (PS), Passive Parallel Synchronous (PPS), JTAG | — |
| Cascading Support | Yes (multi-device daisy chain) | — |
| In-System Programming | IEEE 1532 / JTAG | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Supply Voltage | 3.3 V (5 V tolerant inputs on some revisions) | — |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | — |
| Gehäuse | 100-pin PQFP / EQFP | 100-pin PQFP (T = tape and reel) |
| Montageart | Surface Mount | — |
| Betriebstemperatur | -40C to +85C (industrial) | -40C to +85C (industrial, [DATA_NEEDED: confirm grade]) |
| Page-mode Configuration | Supported | — |
| Compression Support | Altera proprietary bitstream compression | — |
| RoHS-Status | Compliant (Pb-free EQFP) | [DATA_NEEDED: verify from manufacturer page] |
| MSL-Level | 3 (168 hours) | — |
| Modern Replacement Family | EPCS / EPCQ serial flash + Altera generic flash loader | — |
| Product Type | — | Enhanced Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | Enhanced Configuration (EPC) Devices |
| Memory Density | — | [DATA_NEEDED: density in Mbit] |
| Versorgungsspannung | — | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Modes | — | FPP, PPS, PPA, PS, JTAG |
| JTAG Interface | — | IEEE 1149.1 in-system programming |
| Internal Oscillator | — | 50 MHz |
| Multi-Boot Pages | — | Up to 8 configuration pages |
| Page-Mode Read | — | Supported |
| In-System Programmability | — | Yes (continuous, via JTAG) |
| Compatible FPGA Families | — | APEX 20K, APEX II, Mercury, ACEX 1K, Cyclone, Stratix |
| Lead-Free | — | [DATA_NEEDED: verify from manufacturer page] |