EPC80C100 vs EPC80C100T Comparação
Comparação detalhada lado a lado de EPC80C100 por Intel e EPC80C100T por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPC80C100 | EPC80C100T |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $24,10 | $25,40 |
| Device Type | Enhanced Configuration (EPC) Memory | — |
| Configuration Memory Size | 80 Mbit | — |
| Target FPGA Families | Cyclone, Cyclone II, Stratix, APEX 20K, ACEX 1K | — |
| Configuration Modes Supported | Passive Serial (PS), Passive Parallel Synchronous (PPS), JTAG | — |
| Cascading Support | Yes (multi-device daisy chain) | — |
| In-System Programming | IEEE 1532 / JTAG | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Supply Voltage | 3.3 V (5 V tolerant inputs on some revisions) | — |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | — |
| Encapsulamento | 100-pin PQFP / EQFP | 100-pin PQFP (T = tape and reel) |
| Tipo de montagem | Surface Mount | — |
| Temperatura de operação | -40C to +85C (industrial) | -40C to +85C (industrial, [DATA_NEEDED: confirm grade]) |
| Page-mode Configuration | Supported | — |
| Compression Support | Altera proprietary bitstream compression | — |
| Status RoHS | Compliant (Pb-free EQFP) | [DATA_NEEDED: verify from manufacturer page] |
| Nível MSL | 3 (168 hours) | — |
| Modern Replacement Family | EPCS / EPCQ serial flash + Altera generic flash loader | — |
| Product Type | — | Enhanced Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | Enhanced Configuration (EPC) Devices |
| Memory Density | — | [DATA_NEEDED: density in Mbit] |
| Tensão de alimentação | — | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Modes | — | FPP, PPS, PPA, PS, JTAG |
| JTAG Interface | — | IEEE 1149.1 in-system programming |
| Internal Oscillator | — | 50 MHz |
| Multi-Boot Pages | — | Up to 8 configuration pages |
| Page-Mode Read | — | Supported |
| In-System Programmability | — | Yes (continuous, via JTAG) |
| Compatible FPGA Families | — | APEX 20K, APEX II, Mercury, ACEX 1K, Cyclone, Stratix |
| Lead-Free | — | [DATA_NEEDED: verify from manufacturer page] |