EPC80C100T vs EPC40C100 Vergleich

Detaillierter Direktvergleich von EPC80C100T von Intel und EPC40C100 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC80C100T EPC40C100
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $25,40 $10,50
Product Type Enhanced Configuration Device for SRAM-based LUT FPGAs —
Manufacturer Intel (formerly Altera) —
Family Enhanced Configuration (EPC) Devices —
Memory Density [DATA_NEEDED: density in Mbit] 40 Mbit
Versorgungsspannung 3.0 V to 3.6 V (3.3 V typical) —
Configuration Modes FPP, PPS, PPA, PS, JTAG —
JTAG Interface IEEE 1149.1 in-system programming —
Internal Oscillator 50 MHz —
Multi-Boot Pages Up to 8 configuration pages —
Page-Mode Read Supported —
In-System Programmability Yes (continuous, via JTAG) —
Gehäuse 100-pin PQFP (T = tape and reel) 100-pin EQFP (Enhanced Quad Flat Pack)
Compatible FPGA Families APEX 20K, APEX II, Mercury, ACEX 1K, Cyclone, Stratix —
Betriebstemperatur -40C to +85C (industrial, [DATA_NEEDED: confirm grade]) —
RoHS-Status [DATA_NEEDED: verify from manufacturer page] Compliant
Lead-Free [DATA_NEEDED: verify from manufacturer page] Yes
Device Family — Enhanced Configuration Device
Target FPGAs — Stratix, Cyclone, APEX, Mercury, ACEX families
Configuration Mode — FPP (Fast Passive Parallel) / PS (Passive Serial)
Interface Voltage — 2.5 V / 3.3 V
Maximum FPP Clock Frequency — 66 MHz
Programmability — In-system programmable (JTAG)
Error Detection — Built-in CRC verification
Betriebstemperaturbereich — -40 C to +85 C (industrial)
Pin Pitch — 0.5 mm
Montageart — Surface Mount
MSL-Level — 3 (168 hours)
Speichertyp — NOR Flash

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