EPC8QI100 vs EPC18QI100 Vergleich

Detaillierter Direktvergleich von EPC8QI100 von Intel und EPC18QI100 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPC8QI100 EPC18QI100
Marke Intel Altera
Kategorie Memory ICs Memory ICs
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,85 $10,40
Speichertyp Flash (NOR, Enhanced Configuration PROM) —
Speichergröße 8 Mbit —
Supply Voltage (Core) 3.3 V —
Supply Voltage (I/O) 3.3 V —
Schnittstelle Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) —
In-System Programmability IEEE Std. 1532 compliant —
Programming Language Jam STAPL —
Boundary Scan JTAG boundary-scan test supported —
Data Compression Yes (increases effective capacity) —
Configuration Controller On-chip, dedicated to Altera FPGAs —
Initiate-Configuration Pin nINIT_CONF (private JTAG instruction) —
Betriebstemperatur -40C to +85C (industrial) —
Gehäuse 100-PQFP (20 x 14 mm) 100-pin PQFP (Plastic Quad Flat Pack)
Montageart Surface Mount Surface Mount
Compatible FPGAs Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX —
RoHS-Status Non-compliant (legacy PQFP, lead-bearing) Compliant (Pb-free part marking)
Manufacturer — Altera (now Intel Programmable Solutions Group)
Device Type — FPGA Configuration PROM (nonvolatile)
Memory Density — 18 Mbit (18,874,368 bits)
Configuration Interface — Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE)
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 5 V tolerant
Programming Interface — JTAG (IEEE 1149.1) in-system programmable
Cascading Support — Yes (via nCASC pin, multi-device chains supported)
Package Dimensions — 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads)
Betriebstemperaturbereich — -40 C to +85 C (industrial)
MSL-Level — [DATA_NEEDED: MSL level]
Lead Finish — Matte tin (lead-free, per Altera Pb-free roadmap)
Configuration Time — [DATA_NEEDED: configuration time at typical DCLK]
End-of-Life Status — Obsolete; replaced by Altera/Intel EPCQ family

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