EPC8QI100 vs EPC18QI100 比較
詳細な並列比較: EPC8QI100 メーカー: Intel および EPC18QI100 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC8QI100 | EPC18QI100 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | Memory ICs | Memory ICs |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.85 | $10.40 |
| メモリタイプ | Flash (NOR, Enhanced Configuration PROM) | — |
| メモリサイズ | 8 Mbit | — |
| Supply Voltage (Core) | 3.3 V | — |
| Supply Voltage (I/O) | 3.3 V | — |
| インターフェース | Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) | — |
| In-System Programmability | IEEE Std. 1532 compliant | — |
| Programming Language | Jam STAPL | — |
| Boundary Scan | JTAG boundary-scan test supported | — |
| Data Compression | Yes (increases effective capacity) | — |
| Configuration Controller | On-chip, dedicated to Altera FPGAs | — |
| Initiate-Configuration Pin | nINIT_CONF (private JTAG instruction) | — |
| 動作温度 | -40C to +85C (industrial) | — |
| パッケージ | 100-PQFP (20 x 14 mm) | 100-pin PQFP (Plastic Quad Flat Pack) |
| 実装タイプ | Surface Mount | Surface Mount |
| Compatible FPGAs | Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX | — |
| RoHS ステータス | Non-compliant (legacy PQFP, lead-bearing) | Compliant (Pb-free part marking) |
| Manufacturer | — | Altera (now Intel Programmable Solutions Group) |
| Device Type | — | FPGA Configuration PROM (nonvolatile) |
| Memory Density | — | 18 Mbit (18,874,368 bits) |
| Configuration Interface | — | Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5 V tolerant |
| Programming Interface | — | JTAG (IEEE 1149.1) in-system programmable |
| Cascading Support | — | Yes (via nCASC pin, multi-device chains supported) |
| Package Dimensions | — | 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads) |
| 動作温度範囲 | — | -40 C to +85 C (industrial) |
| MSLレベル | — | [DATA_NEEDED: MSL level] |
| Lead Finish | — | Matte tin (lead-free, per Altera Pb-free roadmap) |
| Configuration Time | — | [DATA_NEEDED: configuration time at typical DCLK] |
| End-of-Life Status | — | Obsolete; replaced by Altera/Intel EPCQ family |