EPF10K100EQC208-1 vs EPF10K100EQC208-2 Vergleich
Detaillierter Direktvergleich von EPF10K100EQC208-1 von Altera und EPF10K100EQC208-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPF10K100EQC208-1 | EPF10K100EQC208-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $220,00 | $155,85 |
| Series | FLEX 10KE | FLEX 10KE |
| Logic Elements | 4,992 | — |
| Typical Gates | 100,000 | — |
| Total RAM Bits | 49,152 | 49,152 bits |
| Number of LABs/CLBs | 624 | — |
| Number of I/O | 147 | — |
| Gehäuse | 208-BFQFP (PQFP 28x28 mm) | — |
| Package Pin Count | 208 | — |
| Core Supply Voltage | 2.375 V to 2.625 V (2.5 V nominal) | — |
| I/O Supply Voltage | 3.3 V (multi-voltage I/O) | — |
| Betriebstemperatur | 0 C to 70 C (commercial) | 0 C to +70 C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| Logic Family | CMOS (SRAM-based) | — |
| Propagation Delay | 0.6 ns | — |
| Configuration | SRAM (volatile, in-system programmable) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | Yes (IEEE 1149.1 boundary-scan) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance per Altera product label] | [DATA_NEEDED: not in provided source data] |
| Product Type | — | FPGA (Field Programmable Gate Array) |
| Typical Gate Count | — | 100,000 gates |
| Logic Elements (LEs) | — | 4,992 |
| Logic Array Blocks (LABs) | — | 624 |
| Embedded Array Blocks (EABs) | — | 12 x 2,048 bits |
| Maximum User I/O | — | 147 |
| Supply Voltage - Core (VCCINT) | — | 2.375 V to 2.625 V |
| Supply Voltage - I/O (VCCIO) | — | [DATA_NEEDED: VCCIO range, not in source data] |
| Speed Grade | — | -2 |
| Gehäuse / Bauform | — | 208-BFQFP (PQFP, 28x28 mm) |
| Terminal Form | — | Gull Wing |
| Number of Terminals | — | 208 |
| Configuration Method | — | Serial EEPROM / passive serial / JTAG |