EPF10K50RC240-3 vs EPF10K30RC240-3 Vergleich
Detaillierter Direktvergleich von EPF10K50RC240-3 von Altera und EPF10K30RC240-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPF10K50RC240-3 | EPF10K30RC240-3 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $58,75 | $95,00 |
| Series | FLEX 10K | — |
| Family | Flex 10K | FLEX 10K |
| Logic Cells | 2,880 | — |
| Usable Gates (typical) | 50,000 | — |
| Total Gates (max) | 116,000 (per family) | — |
| Logic Array Blocks (LABs) | 360 | 216 |
| Embedded Array Blocks (EABs) | 10 (per family) | 6 |
| User I/Os | 189 | — |
| Maximum Internal Frequency | 125 MHz | 125 MHz (speed grade -3) |
| Propagation Delay | 0.6 ns (typical, per family) | 0.6 ns typical |
| Supply Voltage (Core) | 5 V | — |
| Technology | CMOS | — |
| Gehäuse | 240-RQFP (RQFP-240 with Exposed Pad) | 240-RQFP / 240-BFQFP Exposed Pad |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0 C to +70 C (commercial) | 0C to +70C (Commercial) |
| Configuration Method | JTAG / EPC configuration device | Serial / parallel PROM, JTAG |
| Programming Tool Support | MAX+PLUS II / Quartus (legacy) | — |
| MSL-Level | [DATA_NEEDED: MSL Level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS Status] | Contains lead (non-RoHS) |
| Lead-Free | [DATA_NEEDED: Lead-Free Status] | — |
| Typical Gates | — | 30,000 |
| Logic Elements (LEs) | — | 1,728 |
| Total RAM Bits | — | 12,288 |
| User I/O Pins | — | 189 |
| Process Technology | — | 0.42 um CMOS, SRAM-based |
| Core Supply Voltage | — | 5.0 V (VCCINT) |
| I/O Supply Voltage | — | 3.3 V or 5.0 V (multiVolt I/O) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |