EPF6024AQI240-1N vs EPF6024AQC240-1 Vergleich
Detaillierter Direktvergleich von EPF6024AQI240-1N von Altera und EPF6024AQC240-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPF6024AQC240-1 - FLEX 6000 FPGA, 24K Gates, 240-PQFP | Intel / Altera
EPF6024AQC240-1 ObsoleteSpezifikationsvergleich
| Parameter | EPF6024AQI240-1N | EPF6024AQC240-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,20 | $18,95 |
| Family | FLEX 6000 | — |
| Device Type | SRAM-based FPGA / Loadable PLD | — |
| Typical Gates | 24,000 | 24,000 |
| Logic Elements | 1,960 | — |
| Maximum Logic Elements | [DATA_NEEDED: maximum logic elements count] | — |
| Number of Dedicated Inputs | 4 | — |
| Number of I/O Pins | 199 | — |
| Maximale Taktfrequenz | 172 MHz | — |
| Process Technology | 0.35 micron CMOS SRAM | 0.42 µm CMOS, 4 metal layers, SRAM-based |
| Configuration Method | JTAG (IEEE 1149.1) / SRAM | — |
| Gehäuse | 240-pin PQFP | — |
| Terminal Pitch | 0.500 mm | — |
| Betriebstemperaturbereich | -40 C to +85 C (industrial) | — |
| Speed Grade | -1 (mid) | — |
| Lead-Free (Pb-free) | Yes (N suffix) | — |
| Montageart | Surface Mount | Surface Mount (Gull-Wing leads) |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | unknown | [DATA_NEEDED: rohs status] |
| Device Family | — | FLEX 6000 |
| Logic Elements / Cells | — | 1,960 |
| Logic Array Blocks (LABs) | — | 196 |
| User I/Os | — | 199 |
| Number of I/O Banks | — | 4 |
| Maximum Internal Frequency | — | 200 MHz (typical application reference) |
| Supply Voltage (VCCINT / VCCIO) | — | 3.3 V |
| Package Type | — | 240-pin PQFP (240-BFQFP), 32 × 32 mm body, 0.5 mm pitch |
| Betriebstemperatur | — | 0 °C to +85 °C (commercial grade) |
| Configuration Memory | — | SRAM (volatile, requires external configuration device) |
| Boundary Scan / JTAG | — | IEEE 1149.1 compliant |