EPM1270F256I5 vs EPM1270F256 Vergleich
Detaillierter Direktvergleich von EPM1270F256I5 von Altera und EPM1270F256 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM1270F256I5 | EPM1270F256 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,90 | $10,85 |
| Device Family | MAX II | — |
| Series | EPM1270 | — |
| Macrocell Count | 980 | — |
| Logic Elements | 1270 | 1270 |
| User I/O Pins | 212 (max) | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Gehäuse | 256-ball FBGA (FineLine BGA) | 256-Pin FineLine BGA |
| Pin/Package Count | 256 | — |
| Process Technology | 0.18 µm | 0.18 µm |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Pin-to-Pin Delay (tPD) | 6.2 ns | — |
| Betriebstemperatur | -40 °C to +100 °C (industrial, "I") | -40C to +100C (industrial, I5N suffix) |
| Speed Grade | 5 | — |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| Family | — | MAX II |
| Macro Cells (Typical) | — | 980 |
| User I/O (Max) | — | 212 |
| Supply Voltage (Core) | — | 2.5 V / 3.3 V (on-chip regulator) |
| I/O Voltages Supported | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Maximum Frequency | — | 201.1 MHz |
| Configuration Memory | — | Non-volatile flash (instant-on) |
| Vertical Migration | — | Pin-compatible with EPM570F256 and EPM2210F256 |