EPM240GF100C5N vs EPM240GM100C5N Vergleich
Detaillierter Direktvergleich von EPM240GF100C5N von Intel und EPM240GM100C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ AktivSpezifikationsvergleich
| Parameter | EPM240GF100C5N | EPM240GM100C5N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,92 | $4,75 |
| Family | MAX II | MAX II G |
| Logic Elements / Macro Cells | 192 macro cells | — |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | — |
| Maximum Operating Frequency | 201.1 MHz | — |
| User I/Os | 80 | 80 |
| Logic Family | CMOS | — |
| Process Technology | 0.18 um | CMOS, Flash-based |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | — |
| Gehäuse | 100-ball FBGA (11 x 11 mm, 1.0 mm pitch) | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | -40 C to +125 C | -40 C to +125 C |
| Programming Interface | JTAG (IEEE 1149.1) / Jam STAPL | JTAG (IEEE 1149.1) - ISP |
| Configuration Memory | On-chip non-volatile Flash | Non-volatile Flash |
| RoHS-Status | Lead Free, RoHS compliant | — |
| Logic Elements | — | 240 (192 macrocells) |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Ball Pitch | — | 0.5 mm |
| Supply Voltage - Core | — | 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| Lead Free / RoHS | — | Yes / Compliant |
| MSL-Level | — | 3 |