EPM240M100I5N vs EPM240GM100C5N Vergleich
Detaillierter Direktvergleich von EPM240M100I5N von Altera und EPM240GM100C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ AktivSpezifikationsvergleich
| Parameter | EPM240M100I5N | EPM240GM100C5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $4,75 |
| Series | MAX II | — |
| Family | MAX II CPLD | MAX II G |
| Macro Cells | 192 | — |
| Logic Elements | 240 | 240 (192 macrocells) |
| Maximum Internal Frequency | 201.1 MHz | — |
| Propagation Delay (tPD) | 4.7 ns | — |
| On-die Non-volatile Memory | 8 Kbits | — |
| Process Technology | 0.18 µm, 6-layer metal flash | CMOS, Flash-based |
| Core Voltage | 2.5 V / 3.3 V | — |
| I/O Bank Voltages | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User I/O Pins | [DATA_NEEDED: user IO count for MBGA package] | — |
| Gehäuse | 100-MBGA (Micro FineLine BGA) | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| Betriebstemperatur | -40 °C to +100 °C (industrial) | -40 C to +125 C |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) - ISP |
| RoHS-Status | Compliant | — |
| Lead-Free | Yes | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| User I/Os | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Ball Pitch | — | 0.5 mm |
| Supply Voltage - Core | — | 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| Configuration Memory | — | Non-volatile Flash |
| Lead Free / RoHS | — | Yes / Compliant |
| MSL-Level | — | 3 |