EPM240T100I5N vs EPM240T100A5N Vergleich
Detaillierter Direktvergleich von EPM240T100I5N von Intel und EPM240T100A5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM240T100I5N | EPM240T100A5N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,68 | $7,05 |
| Series | MAX II | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements (LE) | 240 | 240 |
| Macrocells | 192 | — |
| User I/O Pins | 80 | — |
| On-chip User Flash Memory (UFM) | 8 Kbits | — |
| Process Technology | 0.18 µm, 6-layer-metal flash | 0.18 µm |
| Gehäuse | TQFP-100 | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Montageart | Surface Mount | Surface Mount |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Bank Supply (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Typical Propagation Delay (tPD) | 7 ns (approx., I5 speed grade) | — |
| Betriebstemperaturbereich | -40 °C to +100 °C (industrial, I-temp) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP |
| RoHS-Status | Compliant | Compliant (Pb-free) |
| Configuration Storage | Non-volatile flash (instant-on, no external PROM) | — |
| Family | — | MAX II |
| Macro Cells | — | 192 |
| User I/O Count | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Versorgungsspannung | — | 2.5 V / 3.3 V |
| I/O Bank Count | — | 4 (multi-voltage) |
| Configuration Memory | — | On-chip Flash (instant-on) |
| Betriebstemperatur | — | 0C to +85C (commercial, "A5N" suffix) |