EPM3064ATC44-7N vs EPM3064ATI44-10NAD Vergleich
Detaillierter Direktvergleich von EPM3064ATC44-7N von Altera und EPM3064ATI44-10NAD von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3064ATI44-10NAD - MAX 3000A 64-Macrocell CPLD 44-TQFP | Altera
EPM3064ATI44-10NAD ObsoleteSpezifikationsvergleich
| Parameter | EPM3064ATC44-7N | EPM3064ATI44-10NAD |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $2,30 | $4,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 64 | — |
| Logic Array Blocks | 2 | — |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 34 | — |
| Anzahl der Pins | 44 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Counter Frequency | 192.3 MHz (-7 grade) | — |
| Supply Voltage (VCC) | 3.3 V | — |
| MultiVolt I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| ISP Standard | IEEE Std. 1532 compliant | — |
| Boundary-Scan Test (BST) | Built-in, JTAG-driven | — |
| Gehäuse | 44-pin TQFP | TQFP-44 |
| Betriebstemperatur | 0°C to +85°C (commercial) | -40C to +85C (Industrial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant | Compliant |
| Macrocells | — | 64 |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| User I/Os (max) | — | 34 |
| Setup Time (tSU) | — | 4.5 ns |
| Core Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| Programming Interface | — | JTAG (IEEE Std. 1532 compliant) |
| In-System Programmable | — | Yes |