EPM3064ATI100-10N vs EPM3064ATC-100-10N Vergleich
Detaillierter Direktvergleich von EPM3064ATI100-10N von Altera und EPM3064ATC-100-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3064ATI100-10N - MAX 3000A CPLD, 64-Macrocell, 100-TQFP | Altera
EPM3064ATI100-10N ✓ AktivSpezifikationsvergleich
| Parameter | EPM3064ATI100-10N | EPM3064ATC-100-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,80 | $2,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Programmable Type | In-System Programmable (ISP) via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM | — |
| Usable Gates | 1,250 | — |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | 2 |
| User I/O | 66 | — |
| Supply Voltage (Core / I/O) | 3.3 V | — |
| Pin-to-Pin Delay (tPD) | 10 ns (-10 speed grade) | 10 ns |
| Maximum Internal Frequency | 227.3 MHz (counter) | — |
| Gehäuse | 100-pin TQFP (industrial) | TQFP-100 |
| Betriebstemperatur | -40 C to +85 C (industrial) | 0C to +70C (commercial) |
| JTAG (IEEE 1149.1) | Yes | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) | — |
| MultiVolt I/O | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing | — |
| Lead-Free Status | Contains Lead | — |
| RoHS-Status | RoHS Non-Compliant | Compliant |
| Macro Cells | — | 64 |
| User I/O Pins | — | 66 |
| Usable Gates (min) | — | 600 |
| Usable Gates (typical) | — | 1,250 |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| In-System Programmability | — | Yes (IEEE 1532 / JTAG 1149.1) |
| Programming Interface | — | 4-pin JTAG (TCK/TMS/TDI/TDO) |
| Montageart | — | Surface Mount |