EPM3128ATC100-10NS vs EPM3128AFC256-7N Vergleich
Detaillierter Direktvergleich von EPM3128ATC100-10NS von Intel und EPM3128AFC256-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3128ATC100-10NS | EPM3128AFC256-7N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,50 | $19,85 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | 128 |
| User I/Os | 80 | 98 |
| Pin-Anzahl | 100 | — |
| Gehäuse | TQFP-100 | 256-BGA (FineLine, FBGA) |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | 3.3 V |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) | 3.3 V or 2.5 V |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V | — |
| Programmability | In-system (ISP), IEEE Std. 1532 | In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1) |
| Boundary Scan | IEEE 1149.1 JTAG | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | — | CMOS EEPROM-based MAX |
| Usable Gates | — | 2,500 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal fMAX | — | 192.3 MHz |
| Logic Family | — | CMOS |